Parallel QR decomposition in LTE-A systems

The QR Decomposition (QRD) of communication channel matrices is a fundamental prerequisite to several detection schemes in Multiple-Input Multiple-Output (MIMO) communication systems. Herein, the main feature of the QRD is to transform the non-causal system into a causal system, where consequently efficient detection algorithms based on the Successive Interference Cancellation (SIC) or Sphere Decoder (SD) become possible. Also, QRD can be used as a light but efficient antenna selection scheme. In this paper, we address the study of the QRD methods and compare their efficiency in terms of computational complexity and error rate performance. Moreover, a particular attention is paid to the parallelism of the QRD algorithms since it reduces the latency of the matrix factorization.Comment: The eleventh IEEE International Workshop on Signal Processing Advances for Wireless Communications, 5 pages, 4 figures, 4 algorithms, 1 tabl

Future High Speed In-Vehicle PLC Networks

International audienceThis paper deals with power line communication in vehicle (PLC). PLC is a very promising communication solution in order to offer future in-vehicle applications without increasing wiring harnesses. We join recent additional measurements which have been carried out using modified indoor PLC modems. These PLC modems are based on the two main technologies, HomePLUG AV and HDPLC

What is about future high speed power line communication systems for in-vehicles networks?

International audienceThis paper deals with alternative automotive networks involved by the X-by-wire and X-tainment applications. New market demands like navigation, multimedia, security, safety and individualized options introduce more and more electronic control units. Furthermore, the automotive industry has to face a great challenge in its transition from mechanical engineering towards mechatronical products. In the last decades, the power line technology has received an increasing attention and spans several applications both in indoor, outdoor and in-vehicle data communications. To fulfil theses demands of intra-car communications, techniques based on power line communication (PLC) seem to be a good candidate. These techniques offer both high data rate and good adequacy with power line properties. This paper revisits the work carried out in using PLC within the automotive domain. Different solutions are discussed and results are given for different applications

Embedded Network Combining CAN, ZigBee and DC-PLC for Motorhome

International audience— Today, the number of motorhomes increases in Europe and North America as they offer greater individual freedom. As motorhome users spend the most of their time in their confined area, it seems essential to develop new solutions that make their life easier. In order to meet the new needs of customers, a new centralized architecture of a control system based on ubiquitous wired and wireless solutions is studied in this paper. The objective of this study is to verify the feasibility of ubiquitous technologies in this original environment. Different measurements have been conducted on a motorhome using Controller Area Networks (CAN), ZigBee and direct current power line communications (DC-PLC). Results have shown that these technologies may be used in a future hybrid control system in a motorhome

Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation

ISBN: 0-7695-2533-4International audienceDynamic and partial reconfiguration of FPGAs enables systems to adapt to changing demands. This paper concentrates on how to take into account specificities of partially reconfigurable components during the high level Adequation Algorithm Architecture process. We present a method which generates automatically the design for both partially and fixed parts of FPGAs

Speed-up run-time reconfiguration implementation on FPGAs

International audienceReconfigurable computing is certainly one of the most important emerging research topics over the last few years, in the field of digital processing architectures. The introduction of run-time reconfiguration (RTR) on FPGAs requires appropriate design flows and methodologies to fully exploit this new functionality. For that purpose we present an automatic design generation methodology for heterogeneous architectures based on Network on Chip (NoC) and FPGAs that eases and speed-up RTR implementation. We focus on how to take into account specificities of partially reconfigurable components during the design generation steps. This method automatically generates designs for both fixed and partially reconfigurable parts of a FPGA with automaticmanagement of the reconfiguration process. Furthermore this automatic design generation enables reconfiguration pre-fetching techniques to minimize reconfiguration latency and buffer merging techniques to minimize memory requirements of the generated design. This concept has been applied to different wireless access schemes, based on a combination of OFDM and CDMA techniques. The implementation example illustrates the benefits of the proposed design methodology

Complexity gain of QR Decomposition based Sphere Decoder in LTE receivers

ISBN: 978-1-4244-2515-0International audienceIt has been widely shown that the Sphere Decoding can be used to find the Maximum Likelihood (ML) solution with an expected complexity that is roughly cubic in the dimensions of the problem. However, the computational complexity becomes prohibitive if the Signal-to-Noise Ratio is too low and/or if the dimension of the problem is too large. That is why another technique denoted as Fixed-complexity Sphere Decoder (FSD) is an interesting approach. This algorithm needs a preprocessing step, and in this paper the QR-Decomposition-based preprocessing technique, which is not inconsequential, will be studied. Two different techniques are exposed, including the classical Gram Schmidt orthonormalization process. Their computational complexities and their impacts on the FSD computational complexity are studied. In the LTE context, the overall computational complexities of the two detection techniques are quantified and are shown to be dependent on the constellation size

Design methodology for runtime reconfigurable FPGA: From high level specification down to implementation

In this paper we present an automatic design generation methodology for heterogeneous architectures composed of processors, DSPs and FPGAs. This methodology is based on an Adequation Algorithm Architecture where application is represented by a control data flow graph and architecture by an architecture graph. We focus on how to take into account specificities of partially reconfigurable components during the adequation process and for the design generation. We present a method which generates automatically the design for both fixed and partially reconfigurable parts of a FPGA. This method uses prefetching technic to minimize reconfiguration latency of runtime reconfiguration and buffer merging to minimize memory requirements of the generated design

Réduction de la Complexité du Décodeur Sphérique grâce à l'Adaptation de la Décomposition QR

National audienceL'objet de cet article est de présenter une nouvelle technique de détection, le décodeur sphérique, qui utilise une Décomposition QR. Dans cet article, la Décomposition QR de Householder, qui permet d'obtenir des coefficients réels positifs sur la diagonale de R, est étudiée, alors que l'approche usuelle emploie la Décomposition QR de Gram Schmidt. Même si cette modification provoque une augmentation de la complexité des calculs de la Décomposition QR par rapport à la technique existante, elle permet de réduire fortement la complexité du Décodeur Sphérique adapté, de telle sorte que la complexité globale est réduite. L'objectif de l'étude est de quantifier la diminution de la complexité globale dans un contexte Long Term Evolution (LTE), le protocole utilisé pour la quatrième génération de téléphones portables, sur une cible Embedded Vector Processor (EVP)

Power Line Communication standards for in-vehicle networks

International audienceThis paper deals with the in-vehicle networks. We propose to study a network which do not need new wires called Power Line Communication (PLC). Indeed, the automotive communication networks has evolved and the electronic devices in-vehicle are widespread. For example, drive-by-wire systems have actuators, engine, sensor and microprocessor to replace mechanical or hydraulic systems in vehicles. Moreover, electronic control unit (ECU) communicates and exchanges data. These needs of data sharing between ECU or between new services like multimedia involve to research new buses of communication with high throughputs. The CAN, LIN and FlexRay are wire protocols of communication usually used in the same vehicles and FlexRay has the highest throughput (10 Mbps). It appears that with the increase of electronic devices there is a wire harness bottleneck. To reduce wires and to have high throughputs (> 10 Mbps), we propose to study the feasibility of PLC indoor standards in-vehicles. PLC are usually used in indoor networks. In this paper, a comparison of two PLC standards with throughput measurements thanks to commercial PLC modem in-vehicle is carried out: HomePlug Av (HPAV) and High Definition Power Line Communication (HD-PLC)